Crystalline silicon provides high solar cell efficiencies, η, of up to approximately 23% in commercial production environments, together with advantages, when compared with thin film solar cells such as CIGS, CdTe, etc., of (a) availability, (b) environmentally friendliness, and (c) demonstrated long lifetimes and associated technology maturity. However, crystalline silicon traditionally has a higher photovoltaic module cost than competitive thin-film panels. (A module is the unit that actually generates power and includes a frame holding a number of solar cells, the latter being electrically connected together in series and then to an inverter.) A large part of this cost comes from the cost of manufacturing the silicon wafers (currently ˜180 μm thick), which includes the cost of polysilicon production, ingot formation, and wafering (wire sawing the ingot and finishing the cut wafers).
Thin film processes (amorphous silicon, CIGS and CdTe) have in recent years evoked excitement because of potentially lower costs than crystalline silicon due to less consumables and large-format, integrated processing. However, in general thin film photovoltaic (PV) modules typically have efficiencies substantially less than that of crystalline silicon modules. A typical mono-crystalline module has an efficiency of 15-16% (with some modules as high as 20%), whereas the best case for thin film modules is currently 11%. In addition, the cost advantages of most thin film processes have not been conclusively demonstrated. As a result, crystalline silicon (both monocrystalline and multicrystalline) commands more than an 80% share of the current PV market, at approximately 14 GW for 2010. (Quantities of PV modules are commonly measured by their total power output in Watts.)
A total installed cost for PV modules of less than $2.50/Wp (Wp is Watt peak, referring to the maximum achievable power) is attractive today since in many parts of the world it represents grid-parity with modest incentives. (Grid parity refers to the cost per Watt from a PV module being the same as the cost per Watt available over an electricity distribution grid, where a typical grid I fed by a multitude of power sources such as coal, oil and gas power stations.
Manufacturers have been particularly effective at reducing the manufacturing costs of conventional crystalline silicon (both monocrystalline and multicrystalline) technologies—silicon PV modules have come down in price from more than $4 per Wp in 2006 to roughly $1.80 per Wp in 2010. The most cost efficient integrated manufacturers of PV wafers, cells and modules currently have costs of goods sold (cost of making PV module, including material, labor and overheads) for a PV module approaching $1.10 per Wp. These cost reductions over the past four years have in part been due to the following technical improvements.
First, silicon usage has been reduced from 10 gins per Watt to roughly 6.5 gms per Watt due to a reduction in the solar cell thicknesses and improved wafer sawing processes with lower kerf losses.
Second, cell efficiencies have been improved by fine line printing, improved front-side reflection and passivation control, higher quality (higher lifetime) materials, etc. The average silicon cell efficiency has increased from approximately 14% to 17%, with a number of manufacturers reporting 18% cell efficiencies for their monocrystalline silicon PV cells.
Third, manufacturing has been more fully integrated—there has been a trend to concatenate the various parts of the silicon PV module manufacturing process (polysilicon, wafer, cell, and module) for greater cost-effectiveness, and there is now world wide access to system integrators and installers. For example, in 2010 integrated manufacturing resulted in a cost structure that gives a COGS for PV modules of approximately $1.10.
It is clear that, for the foreseeable future, single crystal silicon PV modules can continue to be a leader in PV and will compete effectively with thin film PV technologies as grid parity is reached, providing single crystal silicon PV module manufacturing can continue with further cost reductions. However, the source of further cost reductions is not immediately apparent.
PV cell and module costs are approaching asymptotic levels with the deployment of large scale production equipment and single crystal silicon cell efficiencies near 19% have been reached, and further increases in cell efficiency may only be achieved at increased cost.
However, further cost reductions may come from a significant reduction in silicon and wafering costs since they now represent the largest portion of the module cost structure. Silicon and wafering costs would be reduced by (a) further reductions in polysilicon production costs, (b) improvements in the crystal growth processes and/or (c) sawing wafers thinner with high yield and low kerf loss. Similarly, a continuous Czochralski crystal growth process may provide incremental cost improvements, but radical cost reductions are unlikely. However, sawing wafers to less than 180 μm has been plagued by lower yields and disproportionately higher kerf losses, as the wire saw technology starts to reach fundamental mechanical limits. Hence, reduction of silicon usage requires looking at new technologies that can bypass the polysilicon, ingoting, and wafering steps altogether.
A further incentive for bypassing these steps is that polysilicon is currently the step that gates the expansion of silicon PV module production capacity, primarily due to the capital cost associated with the polysilicon step alone. In fact, the capital costs—the one-time set-up costs for manufacturing—for polysilicon, ingoting and wafering dominate the total capital costs for production of silicon PV devices. Not only do polysilicon, ingoting and wafering have the highest capital cost (accounting for approximately $2 per Wp out of a total of $3 per Wp for setting up for production of solar cell modules), they also require the most infrastructure in teens of land, gases, water, etc.
It is evident from the above discussion that the crystalline silicon PV industry has made great strides in reducing cost and remaining competitive with thin film PV. However, to get to unsubsidized grid parity at roughly $0.08 per kWh (which is equivalent to approximately $2 per Wp), the total COGS needs to be reduced to approximately $0.80 per Wp for crystalline silicon PV wafers, which is what is required to get to system installed costs for crystalline silicon PV modules of $2 per Wp. This reduction is difficult for conventional silicon PV technology—a technology that has already benefited from the cost reductions due to mass production and innovations that originate in the conventional silicon semiconductor industry. Hence, it is evident that there is a need for cheaper new processes that can replace the current costly processes associated with polysilicon, ingoting and wafering, along with an attendant decrease in capital costs.
Epitaxial deposition of crystalline silicon substrates for PV module production allows a drastic simplification of the supply chain—eliminating the need for polysilicon, ingoting and wafering. However, the challenge is utilizing an epitaxial deposition process at a cost which is comparable if not lower than traditional processes for manufacturing the single crystal silicon wafers.
Epitaxial deposition of thin films of silicon is a common process step in the fabrication of semiconductor devices such as integrated circuits. To enable a high yield for the integrated circuits, this epitaxial deposition step requires that the deposited silicon is of very high quality with a very stringent thickness uniformity. This can only be achieved at lower deposition rates and therefore most of the semiconductor epitaxial reactors are optimized for highly uniform, low defect deposition rates of 0.1 to 1 μm per min. Today almost all advanced high performance CMOS (complementary metal oxide semiconductor) devices are built on such epitaxial layers.
Most conventional epitaxial batch reactors used in the semiconductor industry depend on diffusion to supply reactants—such as trichlorosilane (TCS) and hydrogen—to the center of wafers which inherently results in a higher concentration of TCS on the wafer edge since the gas flow is typically along the periphery of the wafer stack. Thus in order to maintain within wafer and wafer-to-wafer film thickness uniformity, such reactors have to be run in a reaction-rate limited regime at lower temperatures where deposition rates are much lower. Furthermore, for deposition of thin epitaxial films where film quality and uniformity is very important and the device value can accommodate the high process cost, high temperature epitaxial growth is utilized, typically in a single wafer reactor. In this high temperature process chemical vapor deposition (CVD) of TCS is done under a mass transport limited regime where the growth is dependent on the mass transport of TCS to the reaction surface across a boundary layer. However, high temperature processing of single wafers is cost prohibitive for all except the very high value devices such as cutting edge processors.
To circumvent limitations of reactors which rely on diffusion of reactants, some semiconductor epitaxial reactors are designed to have a constant growth rate across the surface of the wafer by forming a stable boundary layer across which there is a constant availability of precursor species. This is typically achieved using the following techniques.
First, the wafer is rotated, which ensures that the gas velocity and the boundary layers are constant across the wafer surface. However, having to rotate the wafers limits reactor types to either single wafer reactors or small batch reactors.
Second, a sufficient supply of TCS is provided such that the TCS is available in the vicinity of the reactant surface without, incurring precursor depletion. This can be achieved by having multiple precursor gas injection points to flood the deposition chamber with TCS. Consequently, in these reactors the TCS utilization is typically only around 5%.
Third, the temperature of the wafers is typically less than 1050° C., thus the growth rates are less than 1 μm per min. Although higher growth rates can be achieved in these reactors, design constraints due to the requirement for wafer rotation at deposition temperatures generally keeps the operating temperature in the 1,000 to 1,050° C. range. For semiconductors this low deposition rate is acceptable since the thickness uniformity and epitaxial quality in-terms of low defect density are paramount.
Fourth, the substrates must be heated-up to deposition temperature and then cooled-down after deposition is complete—this typically takes one hour and is on top of the deposition time for throughput calculations if done in the deposition chamber. Note that these deposition systems typically utilize inductive heating systems, rated at roughly 200 kW.
FIG. 1 (from Sandra Bau, High-temperature CVD silicon films for crystalline silicon thin-film solar cells, Ph.D. dissertation, University of Konstanz 2003 (see page 18, FIG. 3.4), available at http://kops.ub.uni-konstanz.de/handle/urn:nbn:de:bsz:352-opus-11305) shows a plot of growth rate of silicon from TCS as a function of key variables—the substrate temperature and the TCS to H2 ratio. In the case of semiconductor applications, for which commercial epitaxial reactors have been designed, the growth rate must be controlled with a high degree of accuracy, which requires operation of the process under conditions where fluctuations in temperature and TCS to H2 ratio result in no appreciable change in the deposition rate. Thus, the operating region for commercial semiconductor epitaxy is on the flat part of the curve as indicated in FIG. 1.
The following assumptions are used to estimate the cost of epitaxial deposition of a 180 μm crystalline silicon wafer on a 125 mm substrate, assuming production in a commercial semiconductor epitaxial reactor with an 8 wafer batch capacity. At a 1μm per minute deposition rate (see FIG. 1), and including heat-up and cool-down time of 60 minutes, the total production time is 240 minutes. The throughput of a single system operating with an 8 wafer batch is8×60/240=2 wafers per hour.    The depreciation cost per wafer over a 7 year period and assuming a 90% up-time, a 90% utilization and a $1.2M ASP (application specific product) for the reactor is given by$1.2M/(2×0.9×0.9×24×350×7)=$12.60 per wafer.    The TCS consumed per wafer, at 5% utilization is 650 grams per wafer. Assuming the commercial price of TCS is $3 per kg, the cost of TCS per wafer is $2 per wafer. The total power used to produce a batch of 8 wafers is estimated to be 200 kW, and with a cost of power per wafer of 4¢ per kWh, this gives a cost of power of $1 per wafer. Other gases and consumables are estimated to be approximately $1 per wafer. Consequently, the total cost of epitaxial deposition is estimated to be $16.6 per wafer.
Using epitaxial deposition for producing crystalline silicon wafers for PV modules is attractive since it would allow a drastic simplification of the supply chain, although the cost of the epitaxial deposition must be comparable if not lower than traditional processes for manufacturing the silicon wafers. As described above, the cost of silicon wafers for PV applications needs to be close to $0.80 per wafer. However, using commercial semiconductor epitaxial reactors it is estimated to cost substantially more than this—roughly $16.6 per wafer. Clearly, there is a need for an epitaxial deposition reactor that will bring the cost per wafer down by roughly a factor of 25 or more.